UT9Q512K32

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UT9Q512K32 - UT9Q512K32

QCOTSUT9Q512K32 16Megabit SRAM
Data Sheet August, 2002
FEATURES 25ns maximum volt supply) address access time Asynchronous operation compatible with industry standard 512K SRAMs compatible inputs output levels three-state bidirectional data Typical radiation performance Total dose: 50krads Immune MeV-cm2 TH(0.25) MeV-cm 2/mg Saturated Cross Section (cm2) bit, 5.0E <1E-8 errors/bit-day, Adams geosynchronous heavy Packaging options: 68-lead dual cavity ceramic quad flatpack (CQFP) (weight 7.37 grams) Standard Microcircuit Drawing 5962-01511 compliant part
INTRODUCTION QCOTSUT9Q512K32 Quantified Commercial Off-the-Shelf product high-performance byte (16Mbit) CMOS static multi-chip module (MCM), organized four individual 524,288 SRAMs with common output enable. Memory expansion provided active chip enable (En), active output enable (G), three-state drivers. This device powerdown feature that reduces power consumption more than when deselected. Writing each memory accomplished taking chip enable (En) input write enable inputs LOW. Data eight pins (DQ0 through then written into location specified address pins through Reading from device accomplished taking chip enable (En) output enable while forcing write enable (Wn) HIGH. Under these conditions, contents memory location specified address pins will appear pins. input/output pins placed high impedance state when device deselected HIGH), outputs disabled HIGH), during write operation LOW). Perform accesses making along with common input combination discrete memory die.
A(18:0)
512K
512K
512K
512K
DQ(31:24) DQ3(7:0)
DQ(23:16) DQ2(7:0)
DQ(15:8) DQ1(7:0)
DQ(7:0) DQ0(7:0)
Figure UT9Q512K32 SRAM Block Diagram
DEVICE OPERATION
View
DQ0(0) DQ1(0) DQ2(0) DQ3(0) DQ4(0) DQ5(0) DQ6(0) DQ7(0) DQ0(1) DQ1(1) DQ2(1) DQ3(1) DQ4(1) DQ5(1) DQ6(1) DQ7(1)
DQ0(2) DQ1(2) DQ2(2) DQ3(2) DQ4(2) DQ5(2) DQ6(2) DQ7(2) DQ0(3) DQ1(3) DQ2(3) DQ3(3) DQ4(3) DQ5(3) DQ6(3) DQ7(3)
UT9Q512 three control inputs called Enable (En), Write Enable (Wn), Output Enable (G); address inputs, A(18:0); eight bidirectional data lines, DQ(7:0). Device Enable controls device selection, active, standby modes. Asserting enables device, causes rise active value, decodes address inputs select 524,288 words memory. controls read write operations. During read cycle, must asserted enable outputs. Table Device Operation Truth Table Mode 3-state Data 3-state Data Mode Standby Write Read2 Read
Figure 25ns SRAM Pinout (68)
NAMES A(18:0) DQn(7:0) Address Data Input/Output Enable Write Enable Output Enable Power Ground
Notes: defined "don't care" condition. Device active; outputs disabled.
READ CYCLE combination greater than (min) less than (max) defines read cycle. Read access time measured from latter Device Enable, Output Enable, valid address valid data output. SRAM Read Cycle Address Access figure initiated change address inputs while chip enabled with asserted deasserted. Valid data appears data outputs DQ(7:0) after specified AVQV satisfied. Outputs remain active throughout entire cycle. long Device Enable Output Enable active, address inputs change rate equal minimum read cycle time (tAVAV SRAM read Cycle Chip Enable Controlled Access figure initiated going active while remains asserted, remains deasserted, addresses remain stable entire cycle. After specified ETQV satisfied, eight-bit word addressed A(18:0) accessed appears data outputs DQ(7:0). SRAM read Cycle Output Enable Controlled Access figure initiated going active while asserted, deasserted, addresses stable. Read access time tGLQV unless AVQV tETQV have been satisfied.
WRITE CYCLE combination less than VIL(max) less than VIL(max) defines write cycle. state "don't care" write cycle. outputs placed high-impedance state when eitherG greater than IH(min), when less than (max). Write Cycle Write Enable-controlled Access defined write terminated going high, with still active. write pulse width defined tWLWH when write initiated byWn, ETWH when write initiated Unless outputs have been previously placed highimpedance state byG, user must wait WLQZ before applying data nine bidirectional pins DQ(7:0) avoid contention. Write Cycle Chip Enable-controlled Access defined write terminated latter going inactive. write pulse width defined tWLEF when write initiated ETEF when write initiated going active. initiated write, unless outputs have been previously placed high-impedance state user must wait tWLQZ before applying data eight bidirectional pins DQ(7:0) avoid contention.
TYPICAL RADIATION HARDNESS UT9Q512K32 SRAM incorporates features which allows operation limited radiation environment. Table Radiation Hardness Design Specifications Total Dose Heavy Error Rate2 <1E-8 krad(Si) Errors/Bit-Day
Notes: SRAM will latchup during radiation exposure under recommended operating conditions. worst case particle environment, Geosynchronous orbit, mils Aluminum.
ABSOLUTE MAXIMUM RATINGS1 (Referenced SYMBOL TSTG PARAMETER supply voltage Voltage Storage temperature Maximum power dissipation Maximum junction temperature Thermal resistance, junction-to-case3 input current LIMITS -0.5 7.0V -0.5 7.0V +150°C 1.0W (per byte) +150°C 10°C/W
Notes: Stresses outside listed absolute maximum ratings cause permanent damage device. This stress rating only, functional operation device these other conditions beyond limits indicated operational sections this specification recommended. Exposure absolute maximum rating conditions extended periods affect device reliability performance. Maximum junction temperature increased +175°C during burn-in steady-static life. Test MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER Positive supply voltage Case temperature range input voltage LIMITS 5.5V +125°C
ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (-40°C +125°C) 5.0V 10%) SYMBOL VOH1 VOH2 PARAMETER High-level input voltage Low-level input voltage Low-level output voltage Low-level output voltage High-level output voltage High-level output voltage Input capacitance Bidirectional capacitance Input leakage current Three-state output leakage current 8mA, =4.5V 200µA,VDD =4.5V -4mA,VDD =4.5V 200µA,V =4.5V 1MHz 1MHz VSS, (max) (max) (max) (OP) Short-circuit output current (max), (max), Inputs: 0.8V, 2.0V IOUT (max) DD1(OP) Supply current operating @40MHz (per byte) Inputs: 0.8V, 2.0V IOUT (max) IDD2 (SB) Supply current standby @0MHz (per byte) Inputs: IOUT 0.5, (max) 0.5V
Notes: Post-radiation performance guaranteed 25°C MIL-STD-883 Method 1019 Measured only initial qualification after process design changes that could affect input/output capacitance. Supplied design limit guaranteed tested. more than output shorted time maximum duration second.
CONDITION
UNIT
0.08
Supply current operating 1MHz (per byte)
-40°C 25°C 125°C
CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)* (-40°C +125°C) 5.0V 10%) SYMBOL tAVAV tAVQV tAXQX tGLQX tGLQV tGHQZ tETQX tETQV tEFQZ Read cycle time Read access time Output hold time G-controlled Output Enable time G-controlled Output Enable time (Read Cycle G-controlled output three-state time En-controlled Output Enable time En-controlled access time En-controlled output three-state time PARAMETER UNIT
Notes: Post-radiation performance guaranteed MIL-STD-883 Method 1019. Functional test. Three-state defined 500mV change from steady-state output voltage. (enable true) notation refers falling edge immunity does affect read parameters. (enable false) notation refers rising edge immunity does affect read parameters.
High Active Levels
Active High Levels
VLOAD 500mV VLOAD VLOAD 500mV
500mV
500mV
Figure 5-Volt SRAM Loading
tAVAV A(18:0)
DQn(7:0)
Previous Valid Data
Valid Data tAVQV
Assumptions: (max) (min)
tAXQX Figure SRAM Read Cycle Address Access
A(18:0) tETQV DQn(7:0) ETQX tEFQZ
DATA VALID
Assumptions: (max) (min)
Figure SRAM Read Cycle Chip Enable -Controlled Access
AVQV A(18:0) tGLQX DQn(7:0) tGLQV
Assumptions: (max) andW (min)
tGHQZ
DATA VALID
Figure SRAM Read Cycle Output Enable-Controlled Access
CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)* (-40°C +125°C) 5.0V 10%) SYMBOL tAVAV tETWH tAVET tAVWL tWLWH tWHAX tEFAX tWLQZ tWHQX2 tETEF tDVWH tWHDX tWLEF tDVEF tEFDX tAVWH tWHWL1 Write cycle time Device Enable write Address setup time write controlled) Address setup time write controlled) Write pulse width Address hold time write controlled) Address hold time Device Enable controlled) controlled three-state time controlled Output Enable time Device Enable pulse width controlled) Data setup time Data hold time Device Enable controlled write pulse width Data setup time Data hold time Address valid write Write disable time PARAMETER UNIT
Notes: Post-radiation performance guaranteed MIL-STD-883 Method 1019. Functional test performed with outputs disabled high). Three-state defined 500mV change from steady-state output voltage.
A(18:0) AVAV2 tAVWH ETWH tAVWL Qn(7:0) tWLQZ Dn(7:0)
Assumptions: (max). (min) then Qn(7:0) will three-state entire cycle. high AVAV cycle. APPLIED DATA
WHWL tWHAX
WLWH
tWHQX
tDVWH
tWHDX
Figure SRAM Write Cycle Write Enable Controlled Access
tAVAV A(18:0) AVET tETEF tEFAX
AVET tETEF tWLEF
APPLIED DATA
tEFAX
Dn(7:0)
WLQZ Qn(7:0)
DVEF
EFDX
Assumptions Notes: (max). (min) then n(7:0) will three-state entire cycle. Either scenario above occur. high AVAV cycle.
Figure SRAM Write Cycle Chip Enable Controlled Access
CMOS DD-0.05V ohms LOAD 1.55V 0.5V
50pF Notes: 50pF including scope probe test socket capacitance. Measurement data output occurs high high transition mid-point (i.e., CMOS input DD/2). Input Pulses
Figure Test Loads Input Waveforms
DATA RETENTION MODE 2.5V 4.5V
Figure Data Retention Waveform
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) Second Data retention Test) SYMBOL PARAMETER tEFR tR1,3 data retention Data retention current (per byte) Chip deselect data retention time Operation recovery time
MINIMUM tAVAV
MAXIMUM -5.0
UNIT
Notes: .2V, other inputs Data retention current 25oC. guaranteed tested. T=-40
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) Second Data Retention Test, TC=-40oC +125oC) SYMBOL tEFR2, tR2, PARAMETER data retention Chip select data retention time Operation recovery time MINIMUM tAVAV MAXIMUM UNIT
Notes: Performed (min) (max). other inputs guaranteed tested.
PACKAGING
Notes: Package shipped with non-conductive strip (NCS). Leads trimmed. Total weight approx. 7.37g.
Figure 68-pin Ceramic FLATPACK
ORDERING INFORMATION 512K32 16Megabit SRAM MCM:
UT9Q512K32
Lead Finish: Gold
Screening: Prototype flow Extended Industrial Temperature Range Flow (-40 +125o
Package Type: 68-lead dual cavity CQFP
Device Type: =25ns access time, 5.0V operation Aeroflex UTMC Core Part Number
Notes: Prototype flow UTMC Manufacturing Flows Document. Devices tested Gold lead finish only. Extended Industrial Temperature Range flow UTMC Manufacturing Flows Document. Devices tested -40°C +125° Radiation neither tested guaranteed. Gold Lead Finish Only.
512K32 16Megabit SRAM MCM:
5962 01511
Lead Finish: Gold
Case Outline: 68-lead dual cavity CQFP Class Designator: Class Class
Device Type access time, 5.0V operation, Extended Industrial Temp (-40oC +125
Drawing Number: 01511 Total Dose none (10krad(Si)) (30krad(Si)) (contact factory) (50krad(Si)) (contact factory) Federal Stock Class Designator: Options
Notes: Total dose radiation must specified when ordering. Gold finish only. Only Extended Industrial temperature -40C +125C. military temp. test available.

UT9Q512K32

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